View LT4180-15_8236390.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

lt 4180 1 4180fb for more information www.linear.com/4180 typical a pplica t ion fea t ures descrip t ion virtual remote sense controller the lt ? 4180 solves the problem of providing tight load regulation over long, highly resistive cables without requiring an additional pair of remote sense wires. this virtual remote sense? device continuously interrogates the line impedance and corrects the power supply output voltage via its feedback loop to maintain a steady voltage at the load regardless of current changes. the lt4180 is a full-featured controller with 5 ma opto- isolator sink capability, under / overvoltage lockout , soft- start and a 1% internal voltage reference. the virtual remote sense feature set includes user-program- mable dither frequency and optional spread spectrum dither. the lt4180 works with any topology and type of isolated or nonisolated power supply, including dc/dc converters and adjustable linear regulators. the lt4180 is available in a 24-lead, ssop package. isolated power supply with virtual remote sense a pplica t ions n tight load regulation with highly resistive cables without requiring remote sense wiring n compatible with isolated and nonisolated power supplies n 1% internal v oltage reference n 5ma sink current capability n soft-correct reduces turn-on transients n undervoltage and overvoltage protection n pin-programmable dither frequency n optional spread spectrum dither n wide v in range: 3.1v to 50v n 24-lead ssop package n 12v high intensity lamps n 28v industrial systems n high power (> 40 watts) cat 5 cable systems n wiring drop cancellation for notebook computer batter y charging n ac and dc adaptors n well-logging and other remote instrumentation n surveillance equipment l, lt , lt c , lt m , linear technology and the linear logo are registered trademarks and virtual remote sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. v load vs v wire cat5e cable line line ov fb div0 div1 v in c osc comp drain sense div2 spread chold1 chold2 chold3 chold4 4180 ta01a run r osc switching regulator v c + ? lt4180 virtual remote sense c l r l r sense v wiring (v) 0 v load (v) 4.97 4.98 4.99 4.96 4.95 0.5 1.51 2 2.5 3 4.92 4.91 4.94 5.00 4.93 4180 tao1b
lt 4180 2 4180fb for more information www.linear.com/4180 p in c on f igura t ion a bsolu t e maxi m u m r a t ings v in ............................................................. C0. 3 v to 52 v sense ....................................................... v in C 0.3 v to v in intvcc , run , fb , ov , rosc , osc, div 0, div 1, div 2, spread , chold 1, chold 2, chold 3, chold 4, drain , comp , guard 2, guard 3, guard 4, v pp ............ C0.3 v to 5.5 v v in pin current ....................................................... 10 ma in tvcc pin current ............................................. C 10 ma cosc pin current .................................................. 3. 3 ma maximum junction temperature .......................... 12 5 c operating junction temperature range ( note 2) e -, i- grades ....................................... C 40 c to 125 c mp - gr ade .......................................... C 55 c to 125 c storage temperature range .................. C 65 c to 125 c (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead narrow plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 intv cc drain comp chold1 guard2 chold2 guard3 chold3 guard4 chold4 fb gnd v in v pp sense run ov spread div0 div1 div2 osc rosc cosc t jmax = 150c, ja = 85c/w o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range lt4180egn#pbf lt4180egn#trpbf lt4180gn 24-lead narrow plastic ssop C40c to 125c lt4180ign#pbf lt4180ign#trpbf lt4180gn 24-lead narrow plastic ssop C40c to 125c lt4180mpgn#pbf lt4180mpgn#trpbf lt4180gn 24-lead narrow plastic ssop C55c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v in operating supply voltage l 3.10 50 v iv in input quiescent current rosc open, cosc open, sense = v in l 1 2 ma v ref reference voltage v chold2 = v chold3 = 1.2v, measured at chold4 during track ?v out clock phase l 1.209 1.197 1.221 1.221 1.233 1.245 v v i lim open-drain current limit with fb = v ref + 200mv, osc stopped with voltage feedback loop closed 5 12 17 ma v ol drain low voltage v in = 3v 0.3 v v intvcc ldo regulator output voltage v in = 5v 3.15 v the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = sense = 5v, unless otherwise noted.
lt 4180 3 4180fb for more information www.linear.com/4180 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. the lt4180e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c, v in = sense = 5v, unless otherwise noted. symbol parameter conditions min typ max units v intvcc ldo regulator output voltage in dropout v in = 2.5v 2.2 v v ov overvoltage threshold rising 1.21 v v ohyst overvoltage input hysteresis v rising C v falling 15 80 mv v run run threshold falling 1.21 v v rhyst run input hysteresis v rising C v falling 15 80 mv i fb input bias current C0.2 0.2 a a v(ratio) current amplifier gain ratio a vl /a vh , a v measured in v/ v 0.891 0.9 0.909 i sense current amplifier input bias current measured at sense with sense = v in C1 1 a a v ?v fb amplifier gain 9.7 10 10.3 v/ v i chold1 track/hold charging current measured at chold1 with v chold1 = 1.2v 60 a i chold2 track/hold charging current measured at chold2 with v chold2 = 1.2v 25 a i chold3 track/hold charging current measured at chold3 with v chold3 = 1.2v 25 a i chold4 track/hold charging current measured at chold4 with v chold4 = 1.5v, v chold2 = 1v, v chold3 = 1.2v 10 a measured at chold4 with v chold4 = 1.5v, v chold2 = 1.4v, v chold3 = 1.2v C200 a i sc soft-correct current measured at chold4 1.5 a i lkg1 track/hold leakage current measured at chold1 with v chold1 = 1.2v 1 a i lkg2 track/hold leakage current measured at chold2 with v chold2 = 1.2v 1 a i lkg3 track/hold leakage current measured at chold3 with v chold3 = 1.2v 1 a i lkg4 track/hold leakage current measured at chold4 with v chold4 = 1.2v 1 a f osc oscillator frequency r osc = 20k, c osc = 1nf 170 200 230 khz g mfb voltage error amplifier transconductance measured from fb to comp, v comp = 2v, osc stopped with voltage feedback loop closed 120 mho g miamp current amplifier transconductance measured from sense to comp, v comp = 2v, osc stopped with current feedback loop closed 700 mho to 125c operating junction temperature range are assured by design characterization and correlation with statistical process controls. the lt4180i is guaranteed over the full C40c to 125c operating junction temperature range. the lt4180mp is guaranteed over the full C55c to 125c operating junction temperature range. note 3. positive current is defined as flowing into a pin.
lt 4180 4 4180fb for more information www.linear.com/4180 typical p er f or m ance c harac t eris t ics i drain vs v drain normal timing spread spectrum timing v load vs v wire load step in 12v linear application load step in buck application v ref vs temperature intv cc vs temperature oscillator frequency vs temperature v wiring (v) 0 v load (v) 4.97 4.98 4.99 4.96 4.95 0.5 1.51 2 2.5 3 4.92 4.91 4.94 5.00 4.93 4180 g07 5ms/div 500ma 200ma 200ma to 500ma load transient 100f load cap v sense 2v/div v load 2v/div i load 200ma/div 4180 g08 r wire = 8 5s/div triggered on chold1 500mv/div c hold1 with 15k pull-down 2v/div osc 4180 g05 1s/div triggered on osc 500mv/div c hold1 with 15k pull-down 2v/div osc 4180 g06 10ms/div v sense 2v/div v load 2v/div 4180 g09 i load 500ma/div 500ma 1.5a r wire = 2.5 500ma to 1.5a load transient 470f load cap temperature (c) ?55 v ref (v) 1.2205 1.2210 1.2215 105 1.2200 1.2195 1.2190 ?35 ?15 5 25 45 65 85 125 4108 g01 temperature (c) ?55 intv cc (v) 3.150 3.160 3.155 3.165 105 3.145 3.140 3.135 ?35 ?15 5 25 45 65 85 125 4108 g02 temperature (c) ?55 frequency (khz) 203.0 203.5 204.0 105 202.5 202.0 201.5 ?35 ?15 5 25 45 65 85 125 4108 g03 r osc = 20k c osc = 1nf v drain (v) 0 i drain (ma) 8 10 12 0.7 6 4 0.2 0.4 0.1 0.9 0.3 0.5 0.8 0.6 1 2 0 14 4180 g04
lt 4180 5 4180fb for more information www.linear.com/4180 p in func t ions intv cc (pin 1): the ldo output. a low esr ceramic capacitor provides decoupling and output compensation. 1f or more should be used. drain (pin 2): open-drain of the output transistor. this pin drives either the led in an opto-isolator, or pulls down on the regulator control pin. comp ( pin 3): gate of the output transistor. this pin allows additional compensation. it must be left open if unused. chold1 (pin 4): connects to track/hold amplifier hold capacitor. the other end of this capacitor should be kelvin connected to gnd. guard2 (pin 5): guard ring drive for chold2. chold2 (pin 6): connects to track/hold amplifier hold capacitor. the other end of this capacitor should be kelvin connected to gnd. guard3 (pin 7): guard ring drive for chold3. chold3 (pin 8): connects to track/hold amplifier hold capacitor. the other end of this capacitor should be kelvin connected to gnd. guard4 (pin 9): guard ring drive for chold4. chold 4 (pin 10): connects to track/hold amplifier hold capacitor. the other end of this capacitor should be kelvin connected to gnd. fb (pin 11): receives the feedback voltage from an exter- nal resistor divider across the main output. an (optional) capacitor to ground may be added to eliminate high frequency noise. the time constant for this rc network should be no greater than 0.1 times the dither frequency. for example, with f dither = 1khz, t = 0.1ms. gnd (pin 12): ground. cosc (pin 13): oscillator timing capacitor. oscillator frequency is set by this capacitor and rosc. for best ac- curacy, the minimum recommended capacitance is 100pf. rosc (pin 14): oscillator timing resistor. oscillator frequency is set by this resistor and cosc. osc (pin 15): oscillator output. this output may be used to synchronize the switching regulator to the virtual remote sense. this is a high current output capable of driving opto-isolators. other isolation methods may also be used with this output. div2 (pin 16): dither division ratio programming pin. div1 (pin 17): dither division ratio programming pin. div0 (pin 18): dither division ratio programming pin. use the following table to program the dither division ratio (f osc / f dither ) table 1. programming the dither division ratio (f osc / f dither ) div2 div1 div0 division ratio 0 0 0 8 0 0 1 16 0 1 0 32 0 1 1 64 1 0 0 128 1 0 1 256 1 1 0 512 1 1 1 1024 for example, f dither = f osc /128 with div 2 = 1 and div1 = div0 = 0. spread (pin 19): spread spectrum enable input. dither phasing is pseudo-randomly adjusted when spread is tied high. ov (pin 20): overvoltage comparator input. this prevents line drop correction when wiring drops would cause ex- cessive switching power supply output voltage. set ov so v reg(max) 1.50v load . run (pin 21): the run pin provides the user with an ac- curate means for sensing the input voltage and program- ming the start-up threshold for the line drop corrector. sense (pin 22): current sense input. this input connects to the current sense resistor. kelvin connect to r sense . v pp (pin 23): connect this pin to intv cc . v in ( pin 24): main supply pin. v in must be locally bypassed to ground. kelvin connect the current sense resistor to this pin and minimize interconnect resistance.
lt 4180 6 4180fb for more information www.linear.com/4180 b lock diagra m 4180 bd corrected _ref + ? gm2 + ? ov + ? uv + ? gm1 track/ hold + ? i amp 22 track/ hold + ? inst amp track/ hold track/ hold 11 6 8 10 track_hi_fb track_low_fb track_delta_fb ref ref ref_ok chold2 fb 5 guard2 7 guard3 9 guard4 12 gnd 4 chold1 chold3 chold4 3 comp 2 drain 21 run 14 rosc 13 cosc 20 ov track_hi_i fb_select overvoltage undervoltage bandgap sense 1 intv cc 24 v in ldo 23 v pp trim circuit hi_gain r lim 19 spread 18 div0 17 div1 16 div2 15 osc spread spectrum clock generator osc mod clk
lt 4180 7 4180fb for more information www.linear.com/4180 o pera t ion voltage drops in wiring can produce considerable load regulation errors in electrical systems (figure 1). as load current, i l , increases the voltage drop in the wiring (i l ? rw ) increases and the voltage delivered to the sys- tem (v l ) drops. the traditional approach to solving this problem, remote sensing, regulates the voltage at the load, increasing the power supply voltage ( v out ) to compensate for voltage drops in the wiring. while remote sensing works well, it does require an additional pair of wires to measure at the load, which may not always be practical. the lt4180 eliminates the need for a pair of remote sense wires by creating a virtual remote sense. virtual remote sensing is achieved by measuring the incremental change in voltage that occurs with an incremental change in current in the wiring (figure 2). this measurement can then be used to infer the total dc voltage drop in the wiring, which can then be compensated for. the virtual remote sense takes over control of the power supply via the feedback pin (v fb ) of the power supply maintaining tight regulation of load voltage, v l . the lt4180 operates by modulating the output current of the regulator and looking at the resulting voltage change. a large output capacitor is placed across the load so the ac impedance at the load is low. [normally, a capacitor appears across the load in remote sensing situations to keep the impedance low at that point]. this capacitor is large enough that the ac impedance at the load is very low compared to the line resistance. when the output current is modulated, any voltage change that appears across the terminals of the lt4180 is due to the resistance in the line since the ac resistance at the load is very low. there are four sample-and-hold capacitors in the lt4180. the operation cycles through several stages to obtain the correction voltage. first, the output voltage is regulated and the control point is sampled and held. the control loop is then switched to a current regulating control loop and the output current is changed by 10%. tw o sample- and-hold currents store the voltage at the high current and low current level of the modulation. this voltage change is the result of a 10% change in current, making the volt- age change 10% of the total drop in the line. the voltage change is amplified by a factor of 10. the amplified voltage change that occurs with the current is again sampled and held and is used as the correction voltage. the correction voltage is summed into the output and this corrects for the line drop. since this correction is actually open-loop, the actual voltage at the load is not measured. the ability of the lt4180 to correct for line drops is dependent upon the accuracy of the computations . the lt4180 can correct better than 50 to 1 for line drops. for example, a 10 v drop in the line becomes a 200mv change at the load. the frequency of the correction cycle can be set from over 32khz down to less than 250 hz, depending on the size of the capacitors in the system. for very large capacitors in high current systems, the dither correction clock would be run more slowly. in simpler systems with smaller output capacitors, the dither can be run at a higher frequency. if the load contains frequencies similar to the dither, beat notes can result between the load and the lt4180. a spread spectrum option on the lt4180 allows the device to change phasing during the correction cycle so that it will not inter fere with load pulses. finally, the lt4180 takes into account all resistances between the lt4180 and the load capacitor. it can correct for cable connections, line resistances and varying contact resistances. by measuring the peak change at the output of the lt4180 one can monitor the impedance between the lt4180 and the load, and detect increasing impedances figure 1. traditional remote sensing figure 2. virtual remote sensing 4180 f02 power wiring i l virtual remote sense power supply + ? rw v out v fb system + ? v l 4180 f01 power wiring i l remote sense wiring power supply + ? rw v out system + ? v l
lt 4180 8 4180fb for more information www.linear.com/4180 introduction the lt4180 is designed to interface with a variety of power supplies and regulators having either an external feedback or control pin. in figure 4, the regulator error amplifier (which is a g m amplifier) is disabled by tying its inverting input to ground. this converts the error amplifier into a constant-current source which is then controlled by the drain pin of the lt4180. this is the preferred method of interfacing because it eliminates the regulator error ampli- fier from the control loop which simplifies compensation and provides best control loop response. a pplica t ions i n f or m a t ion figure 4. nonisolated regulator interface for proper operation, increasing control voltage should correspond to increasing regulator output. for example, in the case of a current mode switching power supply, the control pin ith should produce higher peak currents as the ith pin voltage is made more positive. figure 5. isolated power supply interface figure 6. cascoded drain pin for isolated supplies drain 4180 f04 lt4180 i th or v c regulator + ? drain 4180 f05 lt4180 v c intv cc regulator opto-coupler + ? drain 4180 f06 intv cc lt4180 to v c > 5v comp from degrading contacts. making the capacitor larger can minimize the voltage ripple at the load due to a combination of load regulation and the dither frequency of the lt4180. figure 3 shows the timing diagram for virtual remote sense. a new cycle begins when the power supply and virtual remote sense close the loop around v out ( regulate v out = h ). both v out and i out slew and settle to a new value, and these values are stored in the virtual remote sense ( track v out high = l and track i out = l ). the v out feedback loop is opened and a new feedback loop is set up commanding the power supply to deliver 90% of the previously measured current (0.9 i out ). v out drops to a new value as the power supply reaches a new steady state, and this information is also stored in the virtual remote sense. at this point, the change in output voltage (?v out ) for a figure 3. simplified timing diagram, virtual remote sense v out track ?v out regulate v out track v out high track i out regulate i out low track v out low 4180 f03 isolated power supplies and regulators may also be used by adding an opto-coupler (figure 5). lt4180 output volt- age intv cc supplies power to the opto-coupler led. in situations where the control pin v c of the regulator may exceed 5 v, a cascode may be added to keep the drain pin of the lt4180 below 5 v (figure 6). use a low vt mosfet for the cascode transistor. C10% change in output current has been measured and is stored in the virtual remote sense. this voltage is used during the next virtual remote sense cycle to compensate for voltage drops due to wiring resistance. o pera t ion
lt 4180 9 4180fb for more information www.linear.com/4180 a pplica t ions i n f or m a t ion design procedure the first step in the design procedure is to determine whether the lt4180 will control a linear or switching supply / regulator. if using a switching power supply or regulator, it is recommended that the supply be synchronized to the lt4180 by connecting the osc pin to the sync pin ( or equivalent) of the supply. if the power supply is synchronized to the lt4180, the power supply switching frequency is determined by: f osc = 4 r osc ? c osc recommended values for r osc are between 20 k and 100k (with 30.1 k the optimum for best accuracy) and greater than 100 pf for c osc . c osc may be reduced to as low as 50pf, but oscillator frequency accuracy will be somewhat degraded. the following example synchronizes a 250 khz switching power supply to the lt4180. in this example, start with r osc = 30.1k: c osc = 4 250khz ? 30.1k = 531pf this example uses 470pf. for 250khz: r osc = 4 250khz ? 470pf = 34.04k the closest standard 1% value is 34k. the next step is to determine the highest practical dither frequency. this may be limited either by the response time of the power supply or regulator, or by the propaga- tion time of the wiring connecting the load to the power supply or regulator. first determine the settling time ( to 1% of final value) of the power supply. the settling time should be the worst-case value ( over the whole operating envelope: v in , i load , etc.). f1 = 1 2 ? t settling hz for example, if the power supply takes 1 ms to settle (worst-case) to within 1% of final value: f1 = 1 2 ? 1e C 3 = 500hz next, determine the propagation time of the wiring. in order to ignore transmission line effects, the dither period should be approximately twenty times longer than this. this will limit dither frequency to: f2 = v f 20 ? 1.017ns/ft ? l hz where v f is the velocity factor ( or velocity of propagation), and l is the length of the wiring (in feet). for example, assume the load is connected to a power supply with 1000 ft of cat 5 cable. nominal velocity of propagation is approximately 70%. f2 = 0.7 20 ? 1.017e C 9 ? 1000 = 34.4khz the maximum dither frequency should not exceed f1 or f2 (whichever is less): f dither < min (f1, f2). continuing this example, the dither frequency should be less than 500hz (limited by the power supply). with the dither frequency known, the division ratio can be determined: d ratio = f osc f dither = 250,000 500 = 500 the nearest division ratio is 512 ( set div0 = l, div1 = div2 = h). based on this division ratio, nominal dither frequency will be: f dither = f osc d ratio = 250,000 512 = 488hz after the dither frequency is determined, the minimum load decoupling capacitor can be determined. this load capacitor must be sufficiently large to filter out the dither signal at the load.
lt 4180 10 4180fb for more information www.linear.com/4180 a pplica t ions i n f or m a t ion c load = 2.2 r wire ? 2 ? f dither where c load is the minimum load decoupling capacitance, r wire is the minimum wiring resistance of one conduc- tor of the wiring pair, and f dither is the minimum dither frequency. continuing the example, our cat 5 cable has a maximum 9.38?/100m conductor resistance. maximum wiring resistance is: r wire = 2 ? 1000ft ? 0.305m/ft ? 0.0938?/m r wire = 57.2? with an oscillator tolerance of 15%, the minimum dither frequency is 414.8 hz, so the minimum decoupling capacitance is: c load = 2.2 57.2 ? 2 ? 414.8hz = 46.36f this is the minimum value. select a nominal value to ac- count for all factors which could reduce the nominal, such as initial tolerance, voltage and temperature coefficients and aging. chold capacitor selection and compensation chold1 a 47 nf capacitor will suffice for most applications. a smaller value might allow faster recovery from a sudden load change, but care must be taken to ensure full load p-p ripple at this node is kept within 5mv: chold2 = chold3 = 2.5nf f dither (khz) for a dither frequency of 488hz: chold2 = chold3 = 2.5nf 0.488(khz) = 5.12nf npo ceramic or other capacitors with low leakage and di- electric absorption should be used for all hold capacitors. set chold4 to 1f. this value will be adjusted later. compensation start with a 47 pf capacitor between the comp and drain pins of the lt4180. add an rc network in parallel with the 47pf capacitor , 10 k and 10 nf are good starting values. once the output voltage has been confirmed to regulate at the desired level at no load, increase the load current to the 100% level and monitor the wire current ( dither current) with a current probe. verify the dither current resembles a square wave with the desired dither frequency. if the output voltage is too low, increase the value of the 10 k resistor until some overshoot is observed at the leading edge of the dither current waveform. if the output voltage is still too low, decrease the value of the 10 nf capacitor and repeat the previous step. repeat this process until the full load output voltage increases to within 1% below the no load level. refer to figures 7a, 7 b and 7 c, which show compensation of the 12v 1.5 a buck regulator typical ap- plication on the data sheet. check for proper voltage drop correction over the load range. the dither current should have good half-wave symmetry. namely, the waveform should have similar rise and fall times, enough settling time at top and bottom and minimum to no over/undershoot. 20s/div v load 11.2v i dither 50ma/div 4180 f07a figure 7a. dither current and v out with 10nf, 10k compensation 1.5a load
lt 4180 11 4180fb for more information www.linear.com/4180 a pplica t ions i n f or m a t ion 20s/div v load 11.9v 4180 f07b i dither 500ma/div figure 7b. dither current and v out with 10nf, 37k compensation 1.5a load figure 8a. 500ma to 1a transient response test with chold4 = 25nf chold4 too small figure 7c. dither current and v out with 3.3nf, 28k compensation 1.5a load figure 8b. 500ma to 1a transient response test with chold4 = 47nf nicely damped behavior 20s/div v load 11.9v 4180 f07c i dither 50ma/div set final value of chold4 set the minimum value for chold4, by performing a transient load test of 30% to 60% of the load and set the value of chold4 to where a nicely damped waveform is observed. refer to figures 8a and 8b for an illustration. 10ms/div v load 1v/div 4180 f08a i dither 500ma/div v load 1v/div 4180 f08b i dither 500ma/div after all the chold values have been finalized, check for proper voltage drop correction and converter behavior (start-up, regulation, etc.), over the load and input volt- age ranges. setting output voltage, undervoltage and overvoltage thresholds the run pin has accurate rising and falling thresholds which may be used to determine when virtual remote sense operation begins. undervoltage threshold should never be set lower than the minimum operating voltage of the lt4180 (3.1v). the overvoltage threshold should be set slightly greater than the highest voltage which will be produced by the power supply or regulator: v out(max) = v load(max) + v wire(max) v out(max) should never exceed 1.5 ? v load since the run and ov pins connect to mosfet input comparators, input bias currents are negligible and a com- mon voltage divider can be used to set both thresholds (figure 9).
lt 4180 12 4180fb for more information www.linear.com/4180 a pplica t ions i n f or m a t ion figure 9. voltage divider for output voltage, uvl and ovl the voltage divider resistors can be calculated from the following equations: r t = v ov 200a , r4 = 1.22v 200a where r t is the total divider resistance and v ov is the overvoltage set point. find the equivalent series resistance for r 2 and r 3 (r ser- ies ). this resistance will determine the run voltage level. r series = 1.22 ? r t v uvl ? ? ? ? ? ? ? r4 r1 = r t ? r series ? r4 r3 = 1.22v ? v out(nom) ? r4 r t ? ? ? ? ? ? v out(nom) r t r2 = r series ? r3 where v uvl is the run voltage and v out(nom) is the nominal output voltage desired. for example, with v uvl = 4v , v ov = 7.5 v and v out( nom) = 5 v, r t = 7.5v 200a = 37.5k r4 = 1.22v 200a = 6.1k r series = 1.22v ? 37.5k 4v ? ? ? ? ? ? ? 6.1k = 5.34k r1 = 37.5k ? 5.34k ? 6.1k = 26.06 k r3 = 1.22 v ? 5v ? 6.1k 37.5k ? ? ? ? ? ? 5v 37.5k = 3.05k r2 = r series ? r3 = 2.29 k r sense selection select the value of r sense so that it produces a 100mv voltage drop at maximum load current. for best accuracy, v in and sense should be kelvin connected to this resistor. figure 10. soft-correct operation, c hold4 = 1f r3 fb 4180 f09 run r2 lt4180 r4 ov r1 v in 200ms/div 4180 f08 5v power supply output voltage 10vw power supply input voltage soft-correct operation the lt4180 has a soft-correct function which insures orderly start-up. when the run pin rising threshold is first exceeded ( indicating v in has crossed its undervolt- age lockout threshold), power supply output voltage is set to a value corresponding to zero wiring voltage drop (no correction for wiring). over a period of time (determined by chold4), the power supply output voltage ramps up to account for wiring voltage drops, providing best load- end voltage regulation. a new soft-correct cycle is also initiated whenever an overvoltage condition occurs.
lt 4180 13 4180fb for more information www.linear.com/4180 a pplica t ions i n f or m a t ion using guard rings the lt4180 includes a total of four track/holds in the virtual remote sense path. for best accuracy, all leakage sources on the chold pins should be minimized. at very low dither frequencies, the circuit board layout may include guard rings which should be tied to their respective guard ring drivers. to better understand the purpose of guard rings, a simplified model of hold capacitor leakage ( with and without guard rings) is shown in figure 11. without guard rings, a large difference voltage may exist between the hold capacitor (pin 1) node and adjacent conductors (pin 2) producing substantial leakage current through the leakage resistance (r lkg ). by adding a guard ring driver with approximately the same voltage as the voltage on the hold capacitor node, the difference voltage across r lkg 1 is reduced substantially thereby reducing leakage current on the hold capacitor. figure 12. clock interface for synchronization osc sync 4180 f12 lt4180 regulator figure 11. simplified leakage models (with and without guard rings) 4180 f11 1 2 r lkg with guard ring without guard ring 1 2 r lkg1 r lkg2 spread spectrum operation virtual remote sense functionality relies on sampling techniques. because switching power supplies are com- monly used, the lt4180 uses a variety of techniques to minimize potential interference ( in the form of beat notes which may occur between the dither frequency and power supply switching frequency). besides several types of internal filtering, and the option for virtual remote sense/ power supply synchronization, the lt4180 also provides spread spectrum operation. by enabling spread spectrum operation, low modula - tion index pseudo- random phasing is applied to virtual remote sense timing. this has the effect of converting any remaining narrow-band interference into broadband noise, reducing its effect. increasing voltage correction range correction range may be slightly improved by regulating intv cc to 5 v . this may be done by placing an ldo between v in and intv cc . contact linear technology applications for more information. synchronization linear and switching power supplies and regulators may be used with the lt4180. in most applications regulator interference should be negligible. for those applications where accurate control of interference spectrum is de- sirable, an oscillator output has been provided so that switching supplies may be synchronized to the lt4180 (figure 12). the osc pin was designed so that it may di- rectly connect to most regulators, or drive opto-isolators (for isolated power supplies).
lt 4180 14 4180fb for more information www.linear.com/4180 typical a pplica t ions 12v, 500ma linear regulator 12v, 500ma boost regulator r11 15k 1% r9 5.36k 1% ov fb div0div1 v in intv cc intv cc v pp comp gnd drain div2 chold1 chold2 guard2 guard3 guard4 chold3 chold4 c12 47nf 4180 ta03 run r osc c osc r7 2k 1% sense spread u2 lt4180egn c13 470pf c11 470pf c10 470pf c9 47nf c7 47pf d1 dfls220 l1 4.7h output to wiring and load (100ma minimum) 500ma, 6 max r wire 100f load capacitance vishay ihlp2525cz-11 c3 1f r12 41.7k 1% c8 10nf r5 3.65k 1% r3 61.9k 1% r13 1.5k c4 1f r1 0.2 1% osc gnd v in 5v c6 0.1f r10 84.5k fault shdn v cc sync rt ss clkout gnd gate sw1 sw1 sw1 sw2 sw2 sw2 fb vc u1 lt3581emse r2 191k r6 24.3k r8 10k r4 100k c2 10f 25v c1 4.7f 16v r8 200k ov fb div0div1 v in intv cc intv cc v pp comp gnd drain div2 chold1 chold2 guard2 guard3 guard4 chold3 chold4 c10 33nf 4180 ta02 run r osc c osc r6 2.2k 1% sense spread u2 lt4180egn c11 470pf c9 470pf c8 470pf c7 47nf q1 irlz440 output to wiring and load 500ma 8 max r wire 100f load capacitance c2 1f r9 41.7k 1% r4 3.74k 1% r2 63.4k 1% c3 1f r1 0.2 1% osc gnd v in 20v r3 27k c4 10f 25v c1 4.7f 25v r5 5.36k 1% intv cc c6 330pf q2 vn2222 r7 10k
lt 4180 15 4180fb for more information www.linear.com/4180 typical a pplica t ions 3.3v isolated flyback regulator r17 10.7k 1% r13 5.36k 1% ov fb div0div1 v in v out ss v in v in v in intv cc intv cc2 v pp comp gnd drain div2 t1 4 3 2 1 pulse engineering pa1277nl pa1277nl chold1 chold2 guard2 guard3 guard4 chold3 chold4 c15 0.1f 4180 ta04 run r osc c osc r10 2.74k 1% sense spread u1 lt4180egn c16 470pf c14 470pf c13 470pf c12 47nf c11 47pf d1 bav21w d3 bas516 q1 si4848dy u3 ps2801-1 output to wiring and load 3.3v, 3a 0.4 max r wire 4 470f, aux tpse 477m010r0050 load capacitance c5 1f r15 41.2k 1% c17 15nf r8 523 1% r4 13.3k 1% c6 1f r5 0.033 1% rt fb shdn/ uvlo sync gnd gate vc vc vc sense c7 0.1f r16 36.5k 1% r9 105k 1% intv cc2 intv cc r14 8.66k 1% osc osc v in 18v to 72v gnd 1 2 3 5 6 7 8 5 6 7 8 3 2 d2 ups840 c3 100f 10v 100f 10v r2 10k c2 4700pf c in2 1f 100v c in1 1f 100v r6 9.1k u2 lt3758 emse r12 100 c4 4.7f 50v c18 2200pf 250v v in r3 51.1 1% r7, 1 c8 0.01f r11 1.3k c10 (opt.) r cs1 0.033
lt 4180 16 4180fb for more information www.linear.com/4180 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. .337 ? .344* (8.560 ? 8.738) gn24 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 161718192021222324 15 14 13 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b)
lt 4180 17 4180fb for more information www.linear.com/4180 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 6/11 revised typical applications drawings revised electrical characteristics replaced curves g08 and g09 in typical performance characteristics replaced text for chold capacitor selection and compensation section and deleted power supply current limiting paragraph in applications information section 1, 13, 14, 18 2, 3 4 10, 11 b 4/13 revised schematics 14, 15, 18
lt 4180 18 4180fb for more information www.linear.com/4180 ? linear technology corporation 2010 lt 0413 rev b ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/4180 typical a pplica t ion r ela t e d p ar t s part number description comments lt3581 boost/inverting dc/dc converter with 3.3a switch, soft-start and synchronization 2.5v v in 22v, current mode control, 200khz to 2.5mhz, msop-16e and 3mm 4mm dfn-14 packages lt3685 36v, 2a, 2.4mhz step-down switching regulator 3.6v v in 36v (60v pk ), integrated boost diode, msop-10e and 3mm 3mm dfn packages lt3573 isolated flyback switching regulator with 60v integrated switch 3v v in 40v, up to 7w, no opto-isolator or third winding required, msop-16e package lt3757 boost, flyback, sepic and inverting controller 2.9v v in 40v, current mode control, 100khz to 1mhz programmable operation frequency, msop-10e and 3mm 3mm dfn-10 packages lt3758 boost, flyback, sepic and inverting controller 5.5v v in 100v, current mode control, 100khz to 1mhz programmable operation frequency, msop-10e and 3mm 3mm dfn-10 packages ltc3805/ ltc3805-5 adjustable fixed 70khz to 700khz operating frequency flyback controller v in and v out limited only by external components, msop-10e and 3mm 3mm dfn-10 packages r13 28k 1% r10 5.36k 1% ov fb div0div1 v in v in 22v to 36v gnd v in bd e1 e3 intv cc intv cc intv cc v pp comp gnd drain div2 chold1 chold2 guard2 guard3 guard4 chold3 chold4 c13 47nf 4180 ta05 run r osc c osc r9 2.01k 1% d1 dfls240 d2 cmdsh-3 sense spread lt4180egn c14 330pf c12 470pf c11 470pf c10 47nf c9 47pf ui lt3685edd output to wiring and load 12v, 1.5a 2.5 max r wire 470f load capacitance c4 1f r12 22.1k 1% c15 3.3nf r6 3.65k 1% r4 61.9k 1% vishay 1hlp2020cz-11 c8 1f r1 0.067 1% boost sync rt fb vc sw pg run/sd c7 22f 25v r11 1k c5 0.1f 50v c1 22f 50v c2 1f 50v r3 100k r8 68.1k 1% + intv cc r5 30.1k r7 10k osc c6 0.47f l1, 10h 12v 1.5a buck regulator

▲Up To Search▲

Price & Availability of LT4180-15

	To Download LT4180-15 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .